Multi-Processing on the PF50

During the scanning of a large cache of PF50 related documents a single A2 logic drawing was found. This drawing resonated with an item found somewhat earlier in the PF50 Technical Description (5020591). On sheet 81 that document states that Bit 17 of the second PI demand register is "Multi-Processor". So from around 2007 or so when we received that document we had reason to suspect that the PF50 CPU was at least specified to allow for multiprocessing. That document provides no other cluse as to what Multi-Processing meant in that context.

Word 0 Bit Word 1 Bit
Not used 23 Not used 23
Control Word 22 Real Time Clock 22
Store Parity 21 External Interrupt 21
Reservation Failure 20 Fragmentation Unit 20
Monitor Modes 19 Program Timer Expired 19
Typewriter 18 Illegal In Priority Mode 18
Fast Interface Term. 1 17 Multi-Processor 17
Fast Interface Term. 2 16 Not used 16
Slow Interface Term. 1 15 Not used 15
Slow Interface Term. 2 14 Not used 14
Slow Interface Term. 3 13 Not used 13
Slow Interface Term. 4 12 Not used 12
Slow Interface Term. 5 11 Not used 11
Slow Interface Term. 6 10 Not used 10
Slow Interface Term. 7 9 Not used 9
Slow Interface Term. 8 8 Not used 8
Slow Interface Term. 9 7 Not used 7
Slow Interface Term. 10 6 Not used 6
Slow Interface Term. 11 5 Not used 5
Slow Interface Term. 12 4 Not used 4
Not used 3 Not used 3
Not used 2 Not used 2
Not used 1 Not used 1
Not used 0 Not used 0

Please note that as this data is from a hardware manual, the bit numbers are in the hardware ordering, i.e. the opposite to that used in the user manuals.

Items in italics are items which were not initially understood, Some of them remain as unknowns. It is hoped to be able to describe all of the italicized items in due course. Can anyone help?

Now we had both a document mentioning Multi-processing and a logic diagram with a very relevant title. You can view that drawing here.

 

Last updated: 24-Apr-2025